The present invention relates to the field of electronic circuits, and, more particularly, to electronic circuits having several modules and a system of synchronization to activate each module in turn. It can be applied especially to modular circuits for the processing of high frequency digital data in which there is provision for a multiplexing of the data transmissions of each module.
According to the prior art, there are known ways of synchronizing a modular electronic circuit by routing a common clock signal to the module that has to be activated in the corresponding multiplexing phase. This should make it possible to synchronize the transmissions of data bits coming from each module and to obtain data bits all having the same temporal width.
FIG. 1 shows a modular electronic circuit with a known type of synchronization system. The common clock signal HO is routed towards one of the modules 1, 2, 3 or 4 to be activated by a set 5 of logic gates and. Each gate and performs an AND logic operation between the clock signal HO and an enabling signal V1, V2, V3, or V4 of a respective module. The enabling signals V1, V2, V3 and V4 are given by a control unit 6.
FIGS. 2a, 2b and 2c show timing diagrams of signals of the known synchronization system of FIG. 1, the signals being respectively the primary clock signal HO, the enabling signal V1 of the module V1 and the secondary clock signal H1 applied to the input of this module 1. As illustrated, a synchronization system of this kind has the drawback of retransmitting the voltage peaks and the temporal variations in the enabling signal V1. This destroys the synchronization of the transmissions of data from the modules.
There also exist known systems of synchronization in which there is provision for shaping the enabling signals by monostable latch circuits. These systems using latch circuits again have the drawback of promoting synchronization errors because of non-compressible and erratic switch-over times, with the synchronization errors reaching delays of up to one nanosecond. The implementation of such systems in a synchronous circuit working at a frequency of over 100 MHZ gives rise to errors of synchronization amounting to more than 10% of the cycle of the clock. Such a degree of imprecision cannot be accepted in high frequency electronic circuits wherein each data bit must have a specified temporal width to prevent errors of transmission.
It is an object of the invention to provide a simple system for the synchronization of modular electronic circuits without the drawbacks of the conventional systems described above.
It is an object of the invention to ensure perfect synchronization of all the modules of an electronic circuit of this kind even at very high frequencies, namely frequencies of more than about 100 MHz.
These and other objects are achieved according to the invention by providing an electronic circuit that comprises a series of computation modules capable of the successive processing of the data elements and a control unit delivering successive enabling signals for the modules. Also included is a system for the coordinated activation of the modules comprising synchronization cells having their pace set by a primary clock signal and delivering secondary clock signals controlled intermittently by the enabling signals to respectively activate the modules. The cells include latches for latching the state of each enabling signal associated with a regulator for regulating the periodicity of the change in state of each secondary clock signal and coordinating the changes in states of the secondary clock signals with one another.
According to a first embodiment of the invention, each cell includes a latch circuit for latching a respective enabling signal synchronized by the primary clock signal, means to delay the primary clock signal in such a way as to change state subsequently to an output signal from the latch circuit, and a logic element combining the output signal from the latch circuit with the delayed primary clock signal, and delivering a respective secondary clock signal.
According to specific embodiments of the invention, the means for delaying the primary clock signal may include pairs of logic inverters, delay lines, capacitive circuits or latch circuits. They preferably introduce a delay time approximately equal to the switching time of a latch circuit.
According to preferred embodiments of the invention, each cell may further include another logic element combining the respective enabling signal with the primary clock signal and resetting the latch circuit when the signals are inactive, and/or means to select the enabling signal controlling the latch circuit from among a group of signals comprising an intermittent enabling signal delivered by the control unit and a temporary test signal delivered by a test unit.
The invention can be applied preferably to electronic circuits comprising very high frequency data-processing modules, especially circuits having a primary clock signal frequency of about 100 MHZ. The delay means then introduce transmission delays of about one nanosecond.
Each module preferably comprises an arithmetic control unit and data latching means at input and at output of the unit synchronized by a respective secondary clock signal.
The advantage of the invention is that it makes it possible to obtain perfect periodicity and perfect synchronization of the secondary clock signals applied to the modules, thus ensuring a regular pacing of a data-processing operation, especially the multiplexing of data bits.